Synthesis Engineer

Description

At Ubitium, we believe the best engineering happens when people with different perspectives tackle hard problems together. We welcome applicants from all backgrounds and experiences. What matters most is curiosity, skill, and the drive to build technology that improves the world. If that resonates with you, we’d love to hear from you. Our team members come from some of the best universities in the world and left some of the largest tech companies to build something truly remarkable.

Tasks

Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred.

Requirements

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

Benefits

• Competitive salary plus stock options
• 30+ days of paid vacation
• Relocation support
• Full German social security and universal healthcare
• A modern office
• Free snacks, coffee, and drinks
• Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems.
• A culture where new ideas matter, but so does respect and collaboration.
• Space to grow: pick up new skills, dig into areas that interest you, and shape your own path.
• Get hands-on with real implementations of AI and signal processing – not just slides or buzzwords.
• An inclusive team where different perspectives are valued and everyone contributes.

We are constantly looking for talent. We recruit through multiple channels – friends & colleagues, universities and professors we know, recruiters, conventions, e-mails and LinkedIn. Join us today.

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